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| MM74C08 Quad 2-Input AND Gate October 1987 Revised January 2004 MM74C08 Quad 2-Input AND Gate General Description The MM74C08 employs complementary MOS (CMOS) transistors to achieve wide power supply operating range, low power consumption and high noise margin, these gates provide basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage. No DC power other than that caused by leakage current is consumed during static condition. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND. Features s Wide supply voltage range: 3.0V to 15V s Guaranteed noise margin: 1.0V s High noise immunity: 0.45 VCC (typ.) s Low power TTL compatibility: Fan out of 2 driving 74L s Low power consumption: 10 nW/package (typ.) Ordering Code: Order Number MM74CD8N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Inputs A L L H H H = HIGH Level L = LOW Level Outputs B L H L H Y L L L H Top View (c) 2004 Fairchild Semiconductor Corporation DS005878 www.fairchildsemi.com MM74C08 Absolute Maximum Ratings(Note 1) Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) 260C 700 mW 500 mW 3.0V to 15V 18V Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. -0.3V to VCC + 0.3V -55C to +125C -65C to +150C DC Electrical Characteristics Min/Max limits apply across the guaranteed temperature range, unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage VCC = 5.0V VCC = 10V VCC = 5.0V VCC = 10V VCC = 5.0V, IO = -10 A VCC = 10V, IO = -10 A VCC = 5.0V, IO = 10 A VCC = 10V, IO = 10 A VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V 74C, VCC = 4.75V 74C, VCC = 4.75V 74C, VCC = 4.75V, IO = -360 A 74C, VCC = 4.75V, IO = 360 A 2.4 0.4 VCC - 1.5 0.8 -1.0 0.005 -0.005 0.01 15 4.5 9.0 0.5 1.0 1.0 3.5 8.0 1.5 2.0 V V V V A A A V V V V Min Typ Max Units CMOS/LPTTL INTERFACE OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25C (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC = 10V, VOUT = V CC 8.0 16 mA VCC = 5.0V, VOUT = VCC 1.75 3.6 mA VCC = 10V, VOUT = 0V -8.0 15 mA VCC = 5.0V, VOUT = 0V -1.75 -3.3 mA www.fairchildsemi.com 2 MM74C08 AC Electrical Characteristics Symbol tpd0, tpd1 CIN CPD Parameter Propagation Delay Time to Logical "1" or "0" Input Capacitance Power Dissipation Capacitance (Note 2) Conditions Min Typ 80 40 5.0 14 Max 140 70 Units ns pF pF (MM74C08) TA = 25C, CL = 50 pF, unless otherwise specified VCC = 5.0V VCC = 10V (Note 3) (Note 4) Per Gate Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note-- AN-90. Typical Performance Characteristics Propagation Delay Time vs Load Capacitance MMM74C08 AC Test Circuit Note: Delays measured with input t r, tf = 20 ns Switching Time Waveforms 3 www.fairchildsemi.com MM74C08 Quad 2-Input AND Gate Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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